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CD4034 - 8-Stage Bidirectional Bus Register IC (Original)

CD4034 - 8-Stage Bidirectional Bus Register IC (Original)

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  • Bidirectional parallel data input
  • Parallel or serial inputs/parallel outputs
  • Asynchronous or synchronous parallel data loading
  • Parallel data-input enable on “A” data lines (3-state output)
  • Data recirculation for register expansion
  • Multipackage register expansion
  • Fully static operation dc-to-10 MHz (typ.) at VDD = 10 V
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°C
  • Noise margin (over full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

CD4034 - 8-Stage Bidirectional Bus Register IC

The CD4034 Register IC is a static eight-stage parallel-or serial-input parallel-output register. It can be used to:

1) Bi-directionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Input that controls the operations includes a single-phase CLOCK (CL), A-DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S).

Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, input for SERIAL DATA is also provided.

All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering.

Register expansion can be accomplished by simply cascading CD4034 packages.

The CD4034 types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).


Pinout of CD4034 - 8-Stage Bidirectional Bus Register IC


  • Parallel Input/Parallel Output, Serial Input/Parallel Output, Serial Input/Serial Output Register
  • Shift right/shift-left register
  • Shift right/shift left with parallel loading
  • Address register
  • Buffer register
  • Bus system register with enable parallel lines at bus side
  • Double bus register system
  • Up-Down Johnson or ring counter
  • Pseudo-random code generators
  • Sample and hold register (storage, counting, display)
  • Frequency and phase comparator

Package Includes:

Selected qty of IC - CD4034


Part number CD4034B
Technology Family CD4000
VCC (Min) (V) 3
VCC (Max) (V) 18
Voltage (Nom) (V) 10
F @ nom voltage (Max)(MHz) 8
ICC @ nom voltage (Max)(mA) 0.3
tpd @ nom Voltage (Max)(ns) 240
IOL (Max) (mA) 15
IOH (Max) (mA) -1.5
3-state output No
Rating See Data Sheet
Operating temperature range (C)  -55 to 125

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