74HC393 Dual 4-bit Binary Ripple Counter IC – Dual 4-bit binary counter IC for clock division. -Robocraze
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Dual 4-bit Binary Ripple Counter IC - 74HC393

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Rs. 26
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SKU: TIFIC0115
  • Typical operating frequency: 50 MHz
  • Typical propagation delay: 13 ns (Ck to QA)
  • Wide operating supply voltage range: 2–6V
  • Low input current: <1 µA
  • Low quiescent supply current: 80 µA maximum (74HC Series)
  • Fanout of 10 LS-TTL loads
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74HC393 Dual 4-bit Binary Ripple Counter IC – Dual 4-bit binary counter IC for clock division. -Robocraze
Dual 4-bit Binary Ripple Counter IC - 74HC393
Rs. 26 Rs. 22

Dual 4-bit Binary Ripple Counter IC - 74HC393

Rs. 26 Rs. 22

Dual 4-bit Binary Ripple Counter IC - 74HC393

The 74HC Series 74HC393 is a 14 Pin Dual 4-bit Binary Ripple Counter IC having 2V to 6V Operating Voltage range and 50 Mhz Clock Frequency. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR), and 4 buffered parallel outputs (nQ0 to nQ3).

The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on nMR clears the counter stages and forces the outputs LOW, independent of the state of nCP. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

check out : Dual 4-bit Decade Ripple Counter IC - 74HC390

Pinout:

Pinout Of 74HC393 IC

Package Includes:

  • 1 x IC - 74HC393

Specifications:

Supply Voltage ? 0.5 to + 7.0V
DC Input Voltage ? 1.5 to VCC + 1.5V
DC Output Voltage ? 0.5 to VCC + 0.5V
Clamp Diode Current ± 20 mA
DC Output Current, per pin ± 25 mA
DC VCC or GND Current, per pin ± 50 mA
Storage Temperature Range ? 65°C to + 150 °C
Power Dissipation 500 mW
Lead Temperature 260 °C

1.What is 74HC393?

  • The 74HC393 is a dual 4-stage binary ripple counter. Each counter has a clock input (nCP), a master reset input (nMR), and four buffered parallel outputs (nQ0 to nQ3). On the HIGH-to-LOW transition of nCP, the counter advances.

2.How does 74HC93 counter work?

  • The 74HC93 is made up of four master-slave flip-flops that are internally linked to provide a divide-by-two and a divide-by-eight section. Each section has its own clock input (CP0 and CP1) to initiate counter state changes on the HIGH-to-LOW clock transition.

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