CD4059 Programmable Divide-by-N Counter IC – Divide-by-N counter IC for frequency control. -Robocraze
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CD4059 - Programmable Divide-by-N Counter IC

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Rs. 236
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SKU: TIFIC0074
  • Presettable down-counter
  • Fully static operation
  • Mode-select control of initial decade counting function
  • Master preset initialization
  • Quiescent current specified to 15 volts
  • Max. input leakage current of 1 µA at 15 volts, full package-temperature range
  • 1 volt noise margin, full package-temperature range
  • 5-V and 10-V parametric ratings
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CD4059 Programmable Divide-by-N Counter IC – Divide-by-N counter IC for frequency control. -Robocraze
CD4059 - Programmable Divide-by-N Counter IC
Rs. 236 Rs. 159

CD4059 - Programmable Divide-by-N Counter IC

Rs. 236 Rs. 159

CD4059 - Programmable Divide-by-N Counter IC 

The CD4x Series CD4059 standard "A" Series types are divide-by-N down-counters that can be programmed to divide an input frequency by any number "N" from 3 to 15,999. The output signal is a pulse one clock-cycle wide occurring at a rate equal to the input frequency divided by N. This single output has TTL drive capability. The down-counter is preset by means of 16 jam inputs.

The three Mode-Select Inputs Ka, Kb, and Kc determine the modulus ("divide-by" number) of the first and last counting sections. Every time the first (fastest) counting section goes through one cycle, it reduces by 1 the number that has been preset (jammed) into the three decades of the intermediate counting section and into the last counting section, which consists of flip-flops that are not needed for operating the first counting section.

For example, in the 2 modes, only one flip-flop is needed in the first counting section. Therefore the last counting section has three flip-flops that can be preset to a maximum count of seven with a place value of thousands. If 10 is desired for the first section, Ka is set to 1, Kb to 1, and Kc to 0. Jam Inputs J1, J2, J3, and J4 are used to preset the first counting section and there is no last counting section. The intermediate counting section consists of three cascaded BCD decade (10) counters presettable by means of Jam Inputs J5 through J16.

This device is particularly advantageous in communication digital frequency synthesis (VHF, UHF, FM, AM, etc.) where programmable divide-by-"N" counters are an integral part of the synthesizer phase-locked-loop sub-system. The CD4059 can also be used to perform the synthesizer "Fixed Divide-by-R" counting function. It is also useful in general-purpose counters for instrumentation functions such as totalizers, production counters, and "time-out" timers.

The CD4059B-series types are supplied in 24-lead dual-in-line plastic packages (E suffix), and 24-lead small-outline packages (M and M96 suffixes).

Pinout:

Pinout of CD4059 IC

Applications:

  • Communications digital frequency synthesizers: VHF, UHF, FM, AM, etc.
  • Fixed or programmable frequency division
  • "Time out" timer for consumer-application industrial controls
  • Companion Application Note, ICAN-6374, "Application of the CMOS CD4059A Programmable Divide-by-N Counter in FM and Citizens Band Transceiver Digital Tuners"

Package Includes:

Selected qty of IC - CD4059

Specifications:

Part number CD4059A-MIL
Technology Family CD4000
VCC (Min) (V) 3
VCC (Max) (V) 18
Bits (#) 1
Voltage (Nom) (V) 10
F @ nom voltage (Max) (MHz) 8
ICC @ nom voltage (Max) (mA) 0.03
tpd @ nom Voltage (Max) (ns) 180
IOL (Max) (mA) 1.5
IOH (Max) (mA) -1.5
Function Counter
Type Other
Operating temperature range (C) -55 to 125
Package Group CDIP SB | 24

1.What is a CD4059 IC and what is its function?

  • The CD4059 is a CMOS integrated circuit that includes a divide-by-N binary counter and a 64-bit shift register. It can be used in a variety of electronic applications to implement frequency division, pulse generation, and time delay functions.

2.How does the CD4059 IC work and what are its features? 

  • The CD4059 IC can be programmed to divide the input clock frequency by a factor of 2, 4, 8, 16, 32, 64, 128, or 256 by connecting the appropriate combination of control inputs (C0-C2) to VDD or GND. The divided clock signal is then fed to the shift register, which can be used to generate a specific length pulse train or to implement a time delay. The shift register output is available at the Q0 output and can be further divided by cascading additional CD4059 ICs or other counter circuits. The CD4059 IC has low power consumption, a wide supply voltage range (3V to 18V), and high noise immunity.

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