CD4532 - 8 Bit Priority Encoder IC (Original)
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The CD4x Series CD4532 consists of combinational logic that encodes the highest priority input (D7-D0) to a 3-bit binary code. The eight inputs, D7 through D0, each have an assigned priority; D7 is the highest priority and D0 is the lowest. The priority encoder is inhibited when the chip-enable input EI is low. When EI is high, the binary representation of the highest-priority input appears on output lines Q2-Q0, and the group select line GS is high to indicate that priority inputs are present. The enable-out (EO) is high when no priority inputs are present. If any one input is high, EO is low and all cascaded lower-order stages are disabled.
The CD4532 types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Selected qty of IC - CD4532
| Part number | CD4532B |
| Technology Family | CD4000 |
| VCC (Min) (V) | 3 |
| VCC (Max) (V) | 18 |
| Channels (#) | 1 |
| Voltage (Nom) (V) | 5, 10, 15 |
| F @ nom voltage (Max) (MHz) | 8 |
| ICC @ nom voltage (Max) (mA) | 0.3 |
| tpd @ nom Voltage (Max) (ns) | 110 |
| IOL (Max) (mA) | 1.5 |
| IOH (Max) (mA) | -1.5 |
| Function | Encoder |
| Type | Standard |
| Operating temperature range (C) | -55 to 125 |
| Package Group | PDIP|16 |
| Configuration | 08:04 |
| Bits (#) | 8 |
| Digital input leakage (Max (uA) | 5 |
| ESD CDM (kV) | 0.75 |
| ESD HBM (kV) | 2 |
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