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74HC138 - 3-to-8 line Decoder/Demultiplexer IC

74HC138 - 3-to-8 line Decoder/Demultiplexer IC-Robocraze

74HC138 - 3-to-8 line Decoder/Demultiplexer IC

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  • Typical propagation delay: 20 ns 
  • Wide power supply range: 2V–6V 
  • Low quiescent current: 80 µA maximum (74HC Series) 
  • Low input current: 1 µA maximum 
  • Fanout of 10 LS-TTL loads

74HC138 - 3-to-8 line Decoder/Demultiplexer IC

The 74HC Series 74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The 74HC138 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW.

Two active LOW and one active HIGH enable (G1, G2A, and G2B) are provided to ease the cascading of decoders. The decoder’s outputs can drive 10 low-power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and the ground.

Pinout:

Pinout Of 74HC138 IC

Package Includes:

Selected qty of IC - 74HC138

Specifications:

Supply Voltage (VCC − 0.5 to + 7.0V DC 
Input Voltage (VIN) −0.5V to VDD + 0.5V
Output Voltage (VOUT) − 0.5 to VCC + 0.5V
Clamp Diode Current (IIK, IOK)  ± 20 mA
DC Output Current, per pin (IOUT) ± 25 mA
DC VCC or GND Current, per pin (ICC) ± 50 mA 
Storage Temperature Range (TSTG) − 65°C to + 150°C 
Power Dissipation (PD) (Note 4)  600 mW
S.O. Package only   500 mW
Lead Temperature (TL) (Soldering 10 seconds)  260°C

ADDITIONAL RESOURCES

Related Blogs

1.What is 74HC138 equivalent to?

  • The 74HC138 has the same pinout as the LS138. The device inputs are compatible with normal CMOS outputs and, with pullup resistors, with LSTTL outputs.

2.What is the function of 74HC138?

  • The 74HC138 is a CMOS device with a high speed. When enabled, the device accepts a three-bit binary weighted address on input pins A0, A1, and A2 and produces one active low output with the remaining seven being high.