What is FPGA?
FPGA Field Programmable Gate Array is an integrated circuit which is designed in such a way that it can be configured by the customer. Hence the term “Field Programmable” is there in the name. The configuration of FPGA is done by using Hardware Descriptive Language (HDL) in the same way as ASICs (Application specific Integrated Circuit) are made. One of the most famous and easy HDL is Verilog which we will be using in our FPGA for beginners series.
FPGA contain an array of programmable logic blocks and a hierarchy of reconfigurable interconnects. Logic blocks can be configured to perform different kinds of functions which can be as simple as a logic gate and as complex as microprocessors, etc. FPGAs can be re-programmed and this is the reason why FPGA is so much popular, let’s suppose we are designing a CPU and want it to be sold so rather than directly making ASICs, we can test our design on FPGA and then proceed for the final chip implementation. In this way if there are some errors then it can be corrected and it will save a huge amount of money.
Applications of FPGA
Due to their programmable nature, FPGAs are used a lot. Some of the fields of applications are listed below.
- ASIC Prototyping : ASIC prototyping with FPGAs enables fast and accurate soC system modelling and verification of embedded software.
- Data center : Designed for high-bandwidth, low-latency servers, networking, and storage applications to bring higher value into cloud deployments.
- Medical : For diagnostic, monitoring, and therapy applications, the Virtex FPGA and Spartan FPGA families can be used to meet a range of processing, display, and I/O interface requirements.
- There are many more applications like wireless communication, Aerospace and defence, Audio, Automotive, etc.
Major applications of FPGA
Architecture of FPGA
An FPGA architecture consists of several fundamental elements known as Configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, known as a fabri. It routes signals between CLBs. Input/Output blocks are there to interface FPGA with the external devices. CLBs may be referred to as logic blocks(LB) or a logic element(LE) or logic cell(LC), it depends on the manufacturer.
A single CLB is made of several logic blocks. A lookup table (LUT) is a characteristic feature of an FPGA. An LUT stores a predefined list of logic output for any combination of inputs. LUTs with four to six input bits are widely used. Some other standard logic functions like multiplexer (mux), full adders (FAs) and flip-flops are also very common in a CLB.
Simplified functional diagram of a CLB
The above figure is an example of simplified CLB. It has two three input LUTs a FA a D-flip flop a standard mux with LUT (let it mux1) and two other muxes (between FA and DFF is mux2 and the last one is mux3). This simplified CLB as two modes of operation i.e. normal and arithmetic mode.
In normal mode the LUTs and mux1 are combined and it forms a four-input LUT whereas in arithmetic mode the LUT outputs are fed to FA as input together with a carry input from different CLB. mux2 selects between LUT and FA and mux3 determines whether the operation is asynchronous or synchronous with the FPGA clock via the DFF.
Current day FPGAs have more complex CLBs and they are capable of executing multiple operations with a single block. CLB can combine together to perform more complex functions like multipliers, counters or digital signal processing functions like fourier transform, etc or image processing and the list is endless.
How to Configure?
We have talked a lot about FPGA but how do we configure these tons of CLBs to perform certain operations. FPGA designs begin by defining the required computing tasks in the development tool, then compiling them into a configuration file that contains information on how to hook up the CLBs and other modules. This process is quite similar to software development, the only difference is that here we configure the hardware for the required functionality in spite of running a set of microinstructions on a predefined hardware. For this purpose, we use Hardware Description Language (HDl) such as VHDL or Verilog.
Given below is what the Verilog code looks like:
module LATCH_IF_ELSE(En1, En2, En3, A1, A2, A3, Y);
input En1, En2, En3, A1, A2, A3;
output Y;
reg Y;
always @ (En1 or En2 or En3 or A1 or A3)
begin
if (En1 == 1)
Y = A1;
else if (En2 == 1)
Y = A2;
else
Y = A3;
end
endmodule
Once the FPGA design has been created and verified using HDL the compiler takes this text file and converts it to a configuration file which contains the information about the connections of the components in FPGA. One important thing to keep in mind is that even if the HDL file does not have any error then also it is possible that the FPGA is not configured. One of the reasons for this can be due to the FPGA running out of resources. For example, if we are designing a module which needs 2000 CLBs and the FPGA have only 1500 CLBs, it will not be able to route between components. So for using with FPGA one needs to have knowledge of both hardware and software.
So we are good to go. We will be sharing plenty of video tutorials so that it will be easy for everyone to learn and even a beginner can start with this!!
This blog has been submitted by KRSSG, IIT-Kharagpur under the Robocraze Club Outreach Program.
Author: Anubhav Prasad
