FPGA configuration and Verilog Introduction

Summary

FPGA Configuration and Verilog Introduction

Hello all. We are back with the exciting series of FPGA tutorials for beginners. This is the 3rd blog of the series and in this blog we will discuss how to configure our FPGA for any specific work. As we discussed earlier, FPGA has a large number of configurational logic blocks that are interconnected between each other and we configure it as per the need of our project. FPGA configuration means loading the FPGA chip with configuration data through any external agent and FPGA is in “ON” state.

This process of configuration is divided into three process :-

1. Master mode : In this mode the configurational data is stored in external nonvolatile memories like PROM, Parallel or SPI FLASH. Data is loaded in CLBs during the configuration process to operate as a specific application. The configurational clock is provided by FPGA which is acting in master mode.
2. Slave mode : In this mode, the whole process is controlled by an external agent. The external agent may be a processor or any microcontroller. Clock input is fed through an external agent for slave mode of operation. It can be performed by either serial or parallel method.
3. JTAG mode : This method uses the JTAG interface for downloading prototypes on FPGA. It is very common in on board testing and debugging the hardware. Most commonly used is four-wire JTAG that consist of TDI, TDO, TCK, TMS lines for communication.

   

Method 1

   

Method 2

Method 3

Now that we have seen the various ways of configuring FPGA, I sometimes mentioned configurational data. So the question is What is configurational data?

Configurational data is the data that contains all the information related to our design. We load this data on FPGA and then the FPGA performs any function according to that. So now we will see how to generate this kind of data.

For generating such data we use a tool that is known as HDL (Hardware Descriptive Language). There are two famous HDLs in use, one is verilog and the other is VHDL. Verilog is based on c programming language while VHDL is based on Ada and Pascal language. VHDL is older than Verilog. We will use verilog in this series as it’s easy for beginners to understand this.

Now that we have seen what to use to get the configurational data, we need some environment to write and test our piece of code before directly uploading it onto the hardware. This saves our time and makes the process more efficient. Just like for any programming language we use a text editor and a compiler, here also we will use a verilog simulator for writing and testing our codes. Some of the free available simulators are Icarus Verilog, Verilator, Clever, Verilogger, Veriwell, etc. There are some paid softwares like Xilinx Design suite ISE, etc. I will be using Xilinx ISE through the tutorial but you can use any free software as per your wish.

Now we are all set to learn Verilog

Before Verilog, life was full of schematics. Every circuit design was designed using schematics, regardless of the complexity and time. This was a tedious process and was too prone to error, but after the introduction of Verilog life became a lot more simple. Verilog design cycle is just like any programming language. There are few steps to follow to make efficient codes :

• Specifications
• High level  design
• Low level design
• RTL coding
• Verification
• Synthesis

We first decide our specifications (specs) for the design. The restrictions that we want to put on our design, then we make a block diagram according to our specs which is known as high level design and then we go for low level design also known as micro design. Let’s take an example. We want to make a circuit that performs arithmetic addition and subtraction operation. So we will go step wise and see how it’s done.

• Specifications : Our design needs to do arithmetic operations on two inputs (say 8 bit inputs)
• High level design : We know two inputs will go into some blackbox which have some circuitry and it will give one output, there will be a control signal  for telling whether to add or subtract and a carry signal as shown in the figure below (note we assume carry in to be zero for simplicity).

• Now we will see the low level design. This blackbox named arithmetic block performs a specific task of adding or subtracting two numbers depending on the control signal. So this can be considered a functional block. We can define this block by using modules in verilog. Below is the example of how a module is described.

MODULE : Syntax for defining modules is shown in the figure above. It starts with module and ends with endmodule. Everything inside this block is for the particular module.

PORTS : For any circuit we need inputs and we process then and give outputs. So port declaration is must. Input ports are declared as input {name} and output ports as output {name}. We can declare a bi-directional port too. Syntax for this is inout {name}.

For defining vector signals we use the following syntax input/output/inout {name}[x:y] as shown above A,B are two vector inputs and Y is a vector output. All three are 8 bit long.

Now after specifying the ports we specify the functionalities of the modules. To keep this blog short we will do that in the next blog. Stay tuned and stay safe!!

This blog has been submitted by KRSSG, IIT-Kharagpur under the Robocraze Club Outreach Program.

Author: Anubhav Prasad